Title:
メモリ回路
Document Type and Number:
Japanese Patent JP5932257
Kind Code:
B2
Abstract:
Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.
Inventors:
Jun Oyamauchi
Hirose Yoshitsune
Kazuhiro Tsumura
Inoue Ayako
Hirose Yoshitsune
Kazuhiro Tsumura
Inoue Ayako
Application Number:
JP2011155701A
Publication Date:
June 08, 2016
Filing Date:
July 14, 2011
Export Citation:
Assignee:
SII Semiconductor Corporation
International Classes:
H01L21/336; G11C16/04; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2007088216A | ||||
| JP2008300520A | ||||
| JP2008270550A | ||||
| JP6334190A | ||||
| JP2003347435A | ||||
| JP4107880A | ||||
| JP2009538519A | ||||
| JP2308571A |
Foreign References:
| US20040080982 |