Title:
ディスプレイパネルをディスプレイ送信エンジンに接続する物理層インターフェースについての電力管理
Document Type and Number:
Japanese Patent JP5932935
Kind Code:
B2
Abstract:
By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.
Inventors:
Gopal, Satiana Rayanan
Bus, sanjib
Pradan, Pravas
Lada Krishnan, Prakash Kay.
Bus, sanjib
Pradan, Pravas
Lada Krishnan, Prakash Kay.
Application Number:
JP2014206441A
Publication Date:
June 08, 2016
Filing Date:
October 07, 2014
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G09G3/20; G09G5/00; H04N21/436
Domestic Patent References:
| JP2009187552A | ||||
| JP2008199236A | ||||
| JP2013539123A |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
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