Title:
計算の非決定性の下でのリカバリ及び耐障害
Document Type and Number:
Japanese Patent JP6313907
Kind Code:
B2
Abstract:
A method for promoting fault tolerance and recovery in a computing system including at least one processing node includes promoting availability and recovery of a first processing node, by, at the first processing node, generating first spawn using a spawner that has been assigned a first generation-indicator so that its spawn inherits the first generation indicator, beginning a checkpoint interval to generate nodal recovery information, suspending the spawner from generating spawn, assigning, to the spawner, a second generation-indicator that differs from the first one, resuming the spawner, so that it generates second spawn that inherits the second generation-indicator, controlling an extent to which the second spawn writes to memory, and after committing nodal recovery information acquired during the checkpoint to durable storage, releasing control over the extent to which the second spawn can write to memory.
Inventors:
Stan Phil Craig W.
Application Number:
JP2017519919A
Publication Date:
April 18, 2018
Filing Date:
October 19, 2015
Export Citation:
Assignee:
Avinisio Technology LLC
International Classes:
G06F11/14; G06F9/52
Domestic Patent References:
| JP2003516581A | ||||
| JP2009501366A |
Attorney, Agent or Firm:
Masaki Hirota
Seiji Ozawa
Yusaku Tokai
Kazuhiro Matsuda
Makoto Horiuchi
Masako Yamauchi
Shuichi Sonomoto
Akihiro Yamamura
Satoshi Morikawa
Hiroyuki Tomita
Seiji Ozawa
Yusaku Tokai
Kazuhiro Matsuda
Makoto Horiuchi
Masako Yamauchi
Shuichi Sonomoto
Akihiro Yamamura
Satoshi Morikawa
Hiroyuki Tomita