Title:
集積回路チップパッケージ用のインターポーザ
Document Type and Number:
Japanese Patent JP6447114
Kind Code:
B2
Abstract:
An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.
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Inventors:
Lee Michael
Takuji Yamamoto
Takuji Yamamoto
Application Number:
JP2014262544A
Publication Date:
January 09, 2019
Filing Date:
December 25, 2014
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L25/065; H01L23/12; H01L23/32; H01L23/36; H01L25/07; H01L25/18
Domestic Patent References:
| JP2007067215A | ||||
| JP2012069882A | ||||
| JP2013232022A | ||||
| JP2001274530A |
Foreign References:
| US20130230272 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Takao Kato
Tadahiko Ito
Takao Kato