Title:
埋め込みエピタキシャルファセットにおけるシリサイド及びコンタクトの形成
Document Type and Number:
Japanese Patent JP6503359
Kind Code:
B2
Abstract:
An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
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Inventors:
Kwan Young Rim
James Walter Bratford
Shashank S. Ekbotet
Yoon Sung Choi
James Walter Bratford
Shashank S. Ekbotet
Yoon Sung Choi
Application Number:
JP2016539219A
Publication Date:
April 17, 2019
Filing Date:
December 12, 2014
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H01L21/336; H01L21/28; H01L21/8238; H01L27/092; H01L29/417; H01L29/78
Domestic Patent References:
| JP200871890A | ||||
| JP20119412A |
Foreign References:
| US6358801 | ||||
| US5571733 | ||||
| US20120091539 |
Attorney, Agent or Firm:
Kyozo Katayose