Title:
ハイブリッドメモリキューブリンクを用いる相互接続システムおよび方法
Document Type and Number:
Japanese Patent JP6522663
Kind Code:
B2
Abstract:
System on a Chip (SoC) devices include two packetized memory busses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
Inventors:
Radel, John Dee.
Application Number:
JP2016566810A
Publication Date:
May 29, 2019
Filing Date:
May 01, 2015
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
G06F12/00; G06F13/16; G06F15/173
Domestic Patent References:
| JP2012527036A | ||||
| JP2012514286A | ||||
| JP6187299A | ||||
| JP2000235558A | ||||
| JP2006518885A | ||||
| JP2003076670A |
Foreign References:
| US20100303079 | ||||
| US20100165692 | ||||
| US20110219197 | ||||
| US6970968 | ||||
| US20040088522 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Nomura Yasuhisa
Nomura Yasuhisa