Title:
半導体集積装置のテスト方法及び半導体集積装置
Document Type and Number:
Japanese Patent JP6530166
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated device test method and a semiconductor integrated device in which the manufacturing yield of the semiconductor integrated device can be improved.SOLUTION: A semiconductor integrated device is tested which includes: a first flip-flop that captures a data signal according to a clock signal and supplies it to a logical circuit; and a second flip-flop that captures a signal output from the logical circuit according to a phase shift clock signal which is obtained by shifting the phase of the clock signal, and outputs it. That is, the semiconductor integrated device is made to operate at a clock signal of a first frequency and, if it operates correctly, is determined to be non-defective; and the semiconductor integrated device is made to operate at a clock signal of a second frequency lower than the first frequency and, if it operates correctly, is also determined to be non-defective. In this case, if the semiconductor integrated device does not operate correctly at the clock signal of the second frequency, it is made to operate at the clock signal of the second frequency again in a state where the phase shift amount of the phase shift clock signal is increased in a delay direction; and if it operates correctly, it is determined to be non-defective.
Inventors:
Shuichi Hashidate
Miyazaki Masahiro
Miyazaki Masahiro
Application Number:
JP2014131403A
Publication Date:
June 12, 2019
Filing Date:
June 26, 2014
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP2011158359A | ||||
| JP2005303189A | ||||
| JP2001250920A | ||||
| JP11289321A | ||||
| JP201098351A |
Foreign References:
| US20110221497 | ||||
| WO2009069496A1 |
Attorney, Agent or Firm:
Motohiko Fujimura
Shinji Takano
Shinji Takano