Title:
イントラチップ及びインターチップホッピングバスを介してシステムオンチップ内で及びこれらの間で情報を転送する方法及び装置
Document Type and Number:
Japanese Patent JP6541272
Kind Code:
B2
Abstract:
A system including a first system-on-chip (SoC) and a second SoC. The first SoC includes a first module and a second module. The second module is separate from the first module. The second module is in communication with the first module via a first bus. The first bus is internal to the first SoC. The second SoC is separate from the first SoC. The second SoC is in communication with the first SoC via a second bus. The second bus is external to both the first SoC and the second SoC. The first bus and the second bus are configured to use a same communication protocol to respectively transfer information (i) between the first module and the second module via the first bus and internally within the first SoC and (ii) between the first SoC and the second SoC via the second bus.
Inventors:
Jen, Hong Min
Application Number:
JP2016531042A
Publication Date:
July 10, 2019
Filing Date:
December 09, 2014
Export Citation:
Assignee:
Marvel World Trade Limited
International Classes:
G06F15/17; G06F13/36; H04L45/52
Domestic Patent References:
| JP2009110512A | ||||
| JP2010500641A | ||||
| JP2010152891A |
Other References:
LEE, Kangmin et al.,Low-Power Network-on-Chip for High-Performance SoC Design,IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,米国,IEEE,2006年 2月,VOL. 14, NO. 2,pp. 148-160
Attorney, Agent or Firm:
Longhua International Patent Service Corporation