Title:
高効率熱経路を有する積層半導体ダイアセンブリおよび関連システム
Document Type and Number:
Japanese Patent JP6626083
Kind Code:
B2
Abstract:
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Inventors:
Vadakhkar, Samia, S.
Li, Xiao
Glu Swiss, Stephen K.
Li, Gian
Gandhi, Jaspriet S.
Delderian, James M.
Henbury, David Earl.
Li, Xiao
Glu Swiss, Stephen K.
Li, Gian
Gandhi, Jaspriet S.
Delderian, James M.
Henbury, David Earl.
Application Number:
JP2017501358A
Publication Date:
December 25, 2019
Filing Date:
June 25, 2015
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
H01L23/36; H01L23/34; H01L23/473; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP5013603A | ||||
| JP6500205A | ||||
| JP61253843A | ||||
| JP2008004688A | ||||
| JP7254668A | ||||
| JP1248551A | ||||
| JP11111898A | ||||
| JP2012099612A | ||||
| JP2013222859A | ||||
| JP2009218432A | ||||
| JP61038944U |
Foreign References:
| US20130119528 | ||||
| US20050224953 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Nomura Yasuhisa
Nomura Yasuhisa