Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6647004
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which prevents cost increase and has a sinker layer connected with an embedded layer even in a thick epitaxial layer.SOLUTION: A semiconductor device comprises the steps of: introducing an N type first impurity into a surface of a P type silicon substrate 1 to form a first N type embedded layer 4; introducing an N type second impurity having a diffusion coefficient larger than that of the first impurity into part of the first N type embedded layer 4 to form a second N type embedded layer 6; performing a heat treatment on the P type silicon substrate 1 where the first and second N type embedded layers 4 and 6 are formed; forming a P type impurity-containing P type epitaxial layer 7 on the P type silicon substrate 1; introducing a P type third impurity into a portion of a surface of the P type epitaxial layer 7, which corresponds to a part above the second N type embedded layer 6 to form an N type sinker layer 10; and subsequently performing a heat treatment on the P type silicon substrate 1 thereby to connect the N type sinker layer 10 and the second N type embedded layer 6.SELECTED DRAWING: Figure 2
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Inventors:
Hidenori Mochizuki
Tomohiro Gunji
Tomohiro Gunji
Application Number:
JP2015206406A
Publication Date:
February 14, 2020
Filing Date:
October 20, 2015
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H01L21/336; H01L21/761; H01L29/78
Domestic Patent References:
| JP51043086A | ||||
| JP60133738A |
Foreign References:
| US20100032769 |
Attorney, Agent or Firm:
Tetsuya Mori
Hide Tanaka Tetsu
Hide Tanaka Tetsu