Title:
クロックゲーティングイネーブルの生成
Document Type and Number:
Japanese Patent JP6746791
Kind Code:
B2
Abstract:
In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.
Inventors:
Zawick, Adam Andrew
Application Number:
JP2019531294A
Publication Date:
August 26, 2020
Filing Date:
November 27, 2017
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F1/04; G06F1/3237
Domestic Patent References:
| JP200478581A | ||||
| JP2009284008A | ||||
| JP2004274099A |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada