Title:
スタック型３Ｄメモリ、およびメモリ製造方法
Document Type and Number:
Japanese Patent JP6746868
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a technique for stacking 3D blocks of memory cells.SOLUTION: A memory may include a plurality of memory blocks including first blocks 114 and 104 and second blocks 113 and 103 disposed above the first blocks 114 and 104. In this structure, an insulating layer 123 is disposed between the first blocks 114 and 104 and the second blocks 113 and 103, and it insulates vertical conductors of the memory kernel 104 of the first blocks 114 and 104 from vertical conductors of the memory kernel 103 of the second blocks 113 and 103. Connection conductors are provided adjacent to the memory blocks or over a plurality of regions including only decode elements, in regions except for the memory kernels. The connection conductors 151 to 153 are coupled to a decode element 114 of the first blocks 114 and 104 and a decode element 113 of the second blocks 113 and 103, and allow connection from a memory cell to a peripheral circuit.
Inventors:
Xi Hun Chen
Application Number:
JP2013235173A
Publication Date:
August 26, 2020
Filing Date:
November 13, 2013
Export Citation:
Assignee:
Muang Hong Electronic Co., Ltd.
International Classes:
H01L27/115; H01L21/336; H01L27/10; H01L29/788; H01L29/792
Domestic Patent References:
| JP2010166055A | ||||
| JP2010118659A | ||||
| JP2009266280A |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation