Title:
抵抗変化型素子を備えた記憶回路
Document Type and Number:
Japanese Patent JP6749021
Kind Code:
B2
Abstract:
A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RCi) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.
Inventors:
Hiroki Koike
Tetsuro Endo
Tetsuro Endo
Application Number:
JP2017519363A
Publication Date:
September 02, 2020
Filing Date:
May 16, 2016
Export Citation:
Assignee:
Tohoku University
International Classes:
G11C11/16
Domestic Patent References:
| JP2003317467A | ||||
| JP2003281880A | ||||
| JP2004103202A | ||||
| JP2009238327A | ||||
| JP2013161502A | ||||
| JP2003346475A |
Attorney, Agent or Firm:
Kimura Mitsuru
Hiroyoshi Sato
Hiroyoshi Sato