Title:
配線基板の製造方法
Document Type and Number:
Japanese Patent JP6816722
Kind Code:
B2
Abstract:
To produce a wiring substrate having excellent electrical characteristics with conduction failure in a hole formed in a layer made of a fluororesin material sufficiently suppressed without conducting an etching treatment using metal sodium. A process for producing a wiring substrate, which comprises forming a hole in a laminate comprising a first conductor layer, a layer (A) which is made of a fluororesin material containing a melt-moldable fluororesin having specific functional groups and a reinforcing fiber substrate and which has a dielectric constant from 2.0 to 3.5, a second conductor layer, an adhesive layer and a layer (B) made of a cured product of a thermosetting resin laminated in this order, applying, to an inner wall surface of the hole, either one or both of a treatment with a permanganic acid solution and a plasma treatment without conducting an etching treatment using metal sodium, and then forming a plating layer.
Inventors:
Tomoya Hosoda
Toru Sasaki
Nobutaka Kidera
Tatsuya Terada
Toru Sasaki
Nobutaka Kidera
Tatsuya Terada
Application Number:
JP2017545796A
Publication Date:
January 20, 2021
Filing Date:
October 20, 2016
Export Citation:
Assignee:
AGC Inc.
International Classes:
H05K3/42; C23C18/20; H05K1/03; H05K1/09; H05K3/26
Domestic Patent References:
| JP201151203A | ||||
| JP200755054A | ||||
| JP2008258211A | ||||
| JP2015176921A | ||||
| JP2007118528A |
Attorney, Agent or Firm:
Sumio Tanai
Suzuki Mitsuyoshi
Noriko Yanai
Suzuki Mitsuyoshi
Noriko Yanai