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Title:
半導体デバイス及びその製造方法
Document Type and Number:
Japanese Patent JP6868975
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress a loss of a function of a passivation layer by preventing an electrode from being formed over a wider region than an original through-hole when forming an electrode that penetrates the passivation layer.SOLUTION: A semiconductor laminate 100 is provided, (i) the semiconductor laminate comprising: a semiconductor layer or substrate 10; a passivation layer 20 which is laminated on the semiconductor layer or the substrate and includes a through-hole 25; and a peripheral protective layer 32 which is laminated on the passivation layer in a peripheral region of the through-hole. The semiconductor laminate is characterized in that (ii) metal paste 40 is applied onto the semiconductor laminate in such a manner that the metal paste is brought into contact with the semiconductor layer or the substrate via the through-hole of the passivation layer. A manufacturing method includes the steps of (iii) burning the applied metal paste and forming an electrode which is brought into electrical contact with the semiconductor layer or the substrate via the through-hole of the passivation layer. The peripheral protective layer consists of semiconductor particles, has a width equal to or more than 1 μm and equal to or less than 400 μm and has thickness equal to or more than 0.1 μm and equal to or less than 10 μm.SELECTED DRAWING: Figure 1

Inventors:
Takehito Negishi
Yoshiki Ikeda
Yuka Inoue
Haruhiko Ito
Application Number:
JP2016131151A
Publication Date:
May 12, 2021
Filing Date:
June 30, 2016
Export Citation:
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Assignee:
Teijin Limited
International Classes:
H01L31/0224; H01L21/28; H01L21/768; H01L31/0216
Domestic Patent References:
JP2016058438A
JP2015164183A
Foreign References:
WO2016031927A1
WO2013147202A1
US20130233379
CN102386248A
Attorney, Agent or Firm:
Atsushi Aoki
Shinji Mitsuhashi
Masaru Nakajima
Yoichi Watanabe
Nobuo Sekine