Title:
データ処理装置、及び、データ処理方法
Document Type and Number:
Japanese Patent JP6954840
Kind Code:
B2
Abstract:
The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave. In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.
More Like This:
Inventors:
Makiko Yamamoto
Application Number:
JP2017550057A
Publication Date:
October 27, 2021
Filing Date:
October 27, 2016
Export Citation:
Assignee:
Sony Group Corporation
International Classes:
H03M13/27; H04L27/26
Foreign References:
| WO2015076638A1 | ||||
| US20090296838 |
Other References:
LACHLAN MICHAEL ET AL.,"Modulation and Coding for ATSC 3.0,2015 IEEE INTERNATIONAL SYMPOSIUM on Broadband Multimedia Systems and Broadcasting,2015年06月19日,pages 1 - 5
Attorney, Agent or Firm:
Takashi Nishikawa
Yoshio Inamoto
Yoshio Inamoto