Title:
半導体装置及びパワーオンリセット装置
Document Type and Number:
Japanese Patent JP6955883
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor device capable of generating a power-on reset signal, ensuring power-on reset of the internal circuit, even if there are manufacturing variations, and to provide a power-on reset device.CONSTITUTION: A semiconductor device has a regulator receiving a reference voltage, and generating a constant power supply voltage having a voltage value corresponding to the reference voltage in response to power-up, and a power-on reset circuit generating a power-on reset signal, having a first voltage value for prompting reset from the moment in time of power-up over a prescribed period, and transiting to a second voltage value for prompting reset release upon elapsing a prescribed period from the moment in time of power-up, on the basis of the reference voltage and the constant power supply voltage. The power-on reset circuit includes a drive node, a current difference acquisition part for supplying a first current corresponding to the voltage value of the reference voltage to the drive node, and extracting a second current corresponding to the constant power supply voltage from the drive node, and a comparator for obtaining a power-on reset signal based on the comparison result of the voltage value of the drive node and a prescribed threshold level.SELECTED DRAWING: Figure 3
Inventors:
Seiichiro Sasaki
Application Number:
JP2017067832A
Publication Date:
October 27, 2021
Filing Date:
March 30, 2017
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K17/22; H03K5/08
Domestic Patent References:
| JP200848298A | ||||
| JP2006179139A | ||||
| JP2001148621A | ||||
| JP2016127480A |
Attorney, Agent or Firm:
Motohiko Fujimura
Shinji Takano
Shinji Takano