Title:
遅延回路
Document Type and Number:
Japanese Patent JP7304195
Kind Code:
B2
Abstract:
To provide a highly reliable delay circuit.SOLUTION: A delay circuit 440 includes: a delay unit 440a configured to generate a delayed input signal S12 by delaying an input signal S11 by a variable delay time Thold that is freely set by using a terminal voltage of a delay setting terminal CT; and an inspection unit 440b configured to detect an abnormality in the delay setting terminal CT by inspecting the terminal voltage at the time of the expiration of a predetermined minimum delay time Thold_min, while ensuring the minimum delay time Thold_min. The inspection unit 440b is preferable to fix the delayed input signal S12 to a logic level at the time of abnormality detection, for example, when the abnormality in the delay setting terminal CT is detected. The inspection unit 440b is preferable to determine an expected value of the terminal voltage, at the expiration of the minimum delay time Thold_min, for example. The inspection unit 440b is preferable to count the minimum delay time Thold_min in synchronization with a clock signal CLK at a predetermined frequency, for example.SELECTED DRAWING: Figure 6
Inventors:
Noriyuki Sudo
Application Number:
JP2019081906A
Publication Date:
July 06, 2023
Filing Date:
April 23, 2019
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H03K5/13; H03K17/22
Domestic Patent References:
| JP11312966A | ||||
| JP2009212704A | ||||
| JP2004260566A | ||||
| JP201393679A |
Attorney, Agent or Firm:
Patent Attorney Corporation Sano Patent Office
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