Title:
テンソル計算データフロー加速器半導体回路
Document Type and Number:
Japanese Patent JP7474586
Kind Code:
B2
Abstract:
A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.
Inventors:
pen
Krishna Malladi
Chen Hirotada
Cows
Krishna Malladi
Chen Hirotada
Cows
Application Number:
JP2019213487A
Publication Date:
April 25, 2024
Filing Date:
November 26, 2019
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F17/16; G06F12/06
Domestic Patent References:
| JP2018521374A | ||||
| JP2012064087A |
Foreign References:
| US9779786 | ||||
| WO2017171769A1 | ||||
| US20180253402 |
Other References:
GAO,Mingyu et al.,TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory, ACM SIGARCH Computer Architecture News,米国,ACM,2017年04月04日,Volume 45 Issue 1,pp 751-764
Attorney, Agent or Firm:
Patent Attorney Corporation Kyosei International Patent Office