Document Type and Number:
Japanese Patent JPH021401
Kind Code:
B2
Abstract:
This invention concerns an integrated-circuit amplifier incorporating CMOS (metal oxide semiconductor) technology, which amplifiers are capable of supplying a standardized 600 Ohm load, for example. This amplifier functions in class AB, and its output stage comprises an NPN bipolar transistor and an N-channel MOS transistor, connected in series in the same way as a conventional push-pull stage. The NPN transistor is controlled directly at its base by the signal for amplification. The control grid of the MOS transistor receives the output signal from a differential amplifier, one input of which is connected to the amplifier output S, the other input being connected to the emitter of another bipolar transistor, the base of which receives the signal for amplification.
Inventors:
JAN KUROODO BERUTAIYU
KURISUCHAN PERAN
RUI TARARON
KURISUCHAN PERAN
RUI TARARON
Application Number:
JP16940681A
Publication Date:
January 11, 1990
Filing Date:
October 22, 1981
Export Citation:
Assignee:
RECHUUDO E RA FUABURIKASHION DO SHIRUKYUI ANTEGURU SUPESHIO EFCIS SOC
International Classes:
H03F3/345; H03F3/34; H03F3/347; H03F3/45; H03F3/50
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