Title:
【発明の名称】電気化学的な平面化
Document Type and Number:
Japanese Patent JPH04507326
Kind Code:
A
Abstract:
In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
Inventors:
Burnheart Antony F
Contrini Robert Jay
Contrini Robert Jay
Application Number:
JP50804389A
Publication Date:
December 17, 1992
Filing Date:
July 10, 1989
Export Citation:
Assignee:
THE UNITED STATES OF AMERICA
International Classes:
H01L21/28; C23C18/31; H01L21/3063; H01L21/3205; H01L21/321; H01L21/768; (IPC1-7): H01L21/28; H01L21/306; H01L21/3205
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)