Title:
【発明の名称】多重プロセッサ仮想メモリシステムのための集中化された参照及び変更テーブル
Document Type and Number:
Japanese Patent JPH05503382
Kind Code:
A
Abstract:
In a multi-processor virtual memory system 10 a Reference and Change Table (RCT) 36 is located upon a Memory Control Unit (MCU) 25. The RCT 36 is responsive to accesses to any of the Memory Modules (MMs) 24-26 and generates and maintains status bits indicative of the reference and change activity of all of page frames of the system memory that are accessible by any of the CPUs 12A-12n. In that each of the CPUs 12A-12n has access to the page frames of the system memory each of the CPUs 12A-12n is further enabled, via privileged instructions, to test (read) and reset (clear) over a system bus 16 the memory page frame status bits that are generated and stored by the RCT 36. As such, the RCT provides to multiple data processors a centralized and readily accessible store of status information relating to page frames of the system memory.
Inventors:
Ryan, Robert Pea
Cheung, Kin Lin
Cheung, Kin Lin
Application Number:
JP51110390A
Publication Date:
June 03, 1993
Filing Date:
July 25, 1990
Export Citation:
Assignee:
Ergie semicon company limited
International Classes:
G06F12/08; G06F12/10; G06F12/12; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Kazuo Shamoto (5 outside)