Title:
【発明の名称】半導体チツプの検査方法
Document Type and Number:
Japanese Patent JPH0680708
Kind Code:
B2
Abstract:
PURPOSE:To reduce the time required for discrimination of the adequacy of a semiconductor wafer substantially by a method wherein a parallel chip inspection head which is provided with a testing circuit and standard elements which have the same functions as chips to be inspected which are combined together is contacted with the electrodes provided in parallel along the arrangement of the chips to be inspected. CONSTITUTION:Only one to ten units of standard chips 1 are provided in one wafer. The parts 2 other than the standard chips 1 in the wafer are chips in which electrodes for parallel test are provided. Input signals are supplied from the outside of the wafer through external terminals 3 to the input pins or the input/output pins for the standard chips 1 and the testing circuit for the parallel test. The wafer 4 for the parallel test head is put upon a wafer 5 for evaluation. I/O signals of the functionl element 8 in the standard chip part and I/O signal of the functionl element 10 in the evaluation chip part are inputted to and outputted from the tesing circuit 9 in the parallel test chip part through a wiring 14 and route 19 and the values are compared by the comparator in the testing circuit 9 and, if the results do not agree with each other, an internal flag is set at '1' and an external flag output 21 is outputted. If no flag set, the wafer is judged as acceptable.
Inventors:
NOMURA JUJI
Application Number:
JP8648586A
Publication Date:
October 12, 1994
Filing Date:
April 15, 1986
Export Citation:
Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
G01R31/26; H01L21/66; (IPC1-7): H01L21/66; G01R31/26
Domestic Patent References:
| JP5440082A | ||||
| JP593581Y2 |
Attorney, Agent or Firm:
Akira Kobiji (2 outside)
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