Title:
【発明の名称】パルス幅変調システムのための誤トリガ防止システム
Document Type and Number:
Japanese Patent JPH07507432
Kind Code:
A
Abstract:
An anti-false triggering system for a pulse width modulation system includes a ramp generator for generating a ramp signal having a ramp portion and a rest portion; a latch enable signal generator for providing a latch enable signal only during the ramp portion of the ramp signal; and a pulse edge modulator responsive to the ramp portion of the ramp signal for providing a pulse with at least one of its edges modulated, the pulse edge modulator being enabled by the latch enable signal only during the ramp portion of the ramp signal for suppressing false triggering of the pulse edge modulator during the rest portion of the ramp signal.
Inventors:
Edward Perry, Jordan
Application Number:
JP50066394A
Publication Date:
August 10, 1995
Filing Date:
May 24, 1993
Export Citation:
Assignee:
ANALOG DEVICES,INCORPORATED
International Classes:
H03K7/08; (IPC1-7): H03K7/08
Attorney, Agent or Firm:
Keiichiro Nishikyo (2 outside)