Title:
【発明の名称】伝送時にビデオ信号を処理するための整列法及びその装置
Document Type and Number:
Japanese Patent JPH08512185
Kind Code:
A
Abstract:
PCT No. PCT/FR95/00506 Sec. 371 Date Dec. 19, 1995 Sec. 102(e) Date Dec. 19, 1995 PCT Filed Apr. 18, 1995 PCT Pub. No. WO95/28805 PCT Pub. Date Oct. 26, 1995The process consists in carrying out, via a phase-locked loop controlling a clock frequency, a slaving of a comparison signal to the falling edge of the line synchronization pulse, in decoding at the output of a dot counter integrated into the loop and controlled by the clock, on the one hand a value N triggering the comparison signal and corresponding to a specified position inside the line synchronization pulse relative to its falling edge, on the other hand values triggering the rezeroing of the counter and time signals synchronous with the clock and clocking the digital processing of the video signals sampled at the clock frequency.
Inventors:
Claude chapel
Application Number:
JP52677995A
Publication Date:
December 17, 1996
Filing Date:
April 18, 1995
Export Citation:
Assignee:
Thomson-S.S.F.
International Classes:
H04N5/12; H04N7/171; (IPC1-7): H04N7/167
Attorney, Agent or Firm:
Keiichi Yamamoto