Title:
【発明の名称】重イオンの衝突の影響を受けないメモリ・セル
Document Type and Number:
Japanese Patent JPH08512422
Kind Code:
A
Abstract:
PCT No. PCT/FR94/00287 Sec. 371 Date Dec. 11, 1995 Sec. 102(e) Date Dec. 11, 1995 PCT Filed Mar. 16, 1994 PCT Pub. No. WO94/22143 PCT Pub. Date Sep. 29, 1994A differential memory cell comprises two sets, each including first P-channel, second N-channel and third N-channel transistors, connected in series between a high and a low supply voltage. The gate of one of the N-channel transistors of each set is connected to the output node of the other set. The gate of the other N-channel transistor of each set is connected to the gate of the first transistor of the same set. A fourth P-channel transistor, associated with each set, is connected between the high voltage and the gate of the first transistor of the set. A fifth P-channel transistor, associated with each set, is connected between the gate of the first transistor of the set and a read/write line or the low voltage.
Inventors:
Besodonii
Velasco Lau Lumpur
Velasco Lau Lumpur
Application Number:
JP52071494A
Publication Date:
December 24, 1996
Filing Date:
March 16, 1994
Export Citation:
Assignee:
Center National de la Shellche Santi Fique
International Classes:
G11C11/41; G11C11/412; (IPC1-7): G11C11/41
Attorney, Agent or Firm:
Keiichi Yamamoto