Title:
【発明の名称】低速メモリによるインタリービング
Document Type and Number:
Japanese Patent JPH09509818
Kind Code:
A
Abstract:
A digital signal is interleaved by delaying samples thereof by an integral number times a unit delay in accordance with a cyclically repeated delay pattern (AL91) . . . AL(M) Select lines (AL91) . . . AL(M)) of a memory (HAS) are cyclically activated (HAS) at a cycle rate equal to unit delay. During the activation of a select line, both data is written and read from the memory. The data written comprises a relevant bit of each sample to be delayed in an integral number of sample groups. Each sample group is associated with one delay pattern cycle. The data read (b(1,1,j)@a1 . . . b(1,M,j)@aM . . . b(k,1,j)@a1 . . . b(k,M,j)@aM) comprises a number of bits which is equal to the number of bits written. The bits are read in accordance with the delay pattern. Accordingly, the speed requirements imposed on the memory (MEM) are relatively lax.
Inventors:
De La Rule Antoine
Van der Lair Franciscus Antonius Maria
Van der Lair Franciscus Antonius Maria
Application Number:
JP52032796A
Publication Date:
September 30, 1997
Filing Date:
December 04, 1995
Export Citation:
Assignee:
Philips Electronics Nemrose Fennaught Shap
International Classes:
G11B20/18; H03M13/27; H04H20/46; H04H40/27; H04L1/00; H04L27/26; H04H20/72; (IPC1-7): H03M13/22; H04L1/00
Attorney, Agent or Firm:
Akihide Sugimura (6 others)