Title:
【発明の名称】DSPプロセッサのためのバス割当てシステム
Document Type and Number:
Japanese Patent JPH10505925
Kind Code:
A
Abstract:
Three DSP processors selectively require access to a shared resource, such as an external memory, via a common communication bus. A control unit controls bus assignment to the processors to allow this access. The bus is assigned by default to the control unit rather than a processor.
Inventors:
Spread berry, david john
Irving, Clive Russell
Irving, Clive Russell
Application Number:
JP50997895A
Publication Date:
June 09, 1998
Filing Date:
September 08, 1995
Export Citation:
Assignee:
Ionica International Limited
International Classes:
G06F13/364; (IPC1-7): G06F13/364
Attorney, Agent or Firm:
Takashi Ishida (3 others)