Document Type and Number:
Japanese Patent JPS4827498
Kind Code:
B1
Abstract:
A plurality of semiconductor wafers each containing a junction are plated with aluminum on an N conductivity type surface and stacked between P conductivity type attachment wafers. The stack is heated to bond the wafers, gold is plated onto the endmost wafers, and excess aluminum at the periphery of the stack is removed. The wafer stack is subdivided first into slabs and then the slabs repositioned to close the kerf formed by sawing. The repositioned slabs are then subdivided into unitary dice stacks. The unitary dice stacks are then attached to gold coated leads and freed of surface contaminants by flow etching. The cleaned unitary dice stacks are separately protectively encapsulated to form completed rectifiers by first depositing a passivant over the semiconductive surfaces and then molding a plastic housing around the elements.
Application Number:
JP8632170A
Publication Date:
August 23, 1973
Filing Date:
October 02, 1970
Export Citation:
International Classes:
H01L21/52; H01L21/00; H01L21/60; H01L21/98; H01L23/057; H01L23/31; H01L25/07; (IPC1-7): H01L1/14