Document Type and Number:
Japanese Patent JPS4965706
Kind Code:
A
Abstract:
A circuit arrangement for the transmission of a plurality of binary coded messages and continuous signals over a common channel according to time division multiplex principles is described. A fixed character frame is used, and the characters and continuous signals are rested character by character. Prior to transmission, start and stop signals are separated from the message signal, and they are reinserted at the receiver. Message signals and continuous signals are routed to a first shift register. A start signal identifying circuit operates in response to the presence of a start signal in the first shift register to reset a code counter which records the signal elements of a message signal and restores a phase correcting circuit to its original position. The output signal from the first shift register is applied to a second shift register which has a number of stages corresponding to the number of signal elements in a message signal. The outputs of shift register stages containing information bits are connected in parallel to inputs of stages of a third shift register. The latter shift register contains a further stage for receiving the output of an evaluating circuit which interprets the states of the first and last stages of the second shift register so as to distinguish message signals from continuous signals. The parallel transmission of information signals from the second to the third shift register occurs if the first stage of the second shift register contains a start signal, the code counter has reached its final registration position and the third shift register is not currently being read out. When the multiplexer samples the channel in question, the contents of the third shift register are read out for transmission.
Application Number:
JP9780073A
Publication Date:
June 26, 1974
Filing Date:
August 30, 1973
Export Citation:
International Classes:
H04L5/24; (IPC1-7): H04L5/22