Document Type and Number:
Japanese Patent JPS5011341
Kind Code:
A
Abstract:
A memory array comprising a plurality of nonvolatile, variable threshold storage devices which uses but a single sense amplifier for reading each two adjacent rows of devices in the array together with substrate biasing to selectively control the read, write, and erase operations with a single polarity of voltage, thereby eliminating the need of both positive and negative voltages on the gates of the devices.
Application Number:
JP3706274A
Publication Date:
February 05, 1975
Filing Date:
April 03, 1974
Export Citation:
International Classes:
G11C17/00; G11C7/18; G11C11/34; G11C16/04; (IPC1-7): G11C11/40