Document Type and Number:
Japanese Patent JPS5166736
Kind Code:
A
Abstract:
For driving a plurality of memory cells, a driver circuit, connected to the word driver line of the memory cells, includes a resistive connection, connected between the word line and ground potential, for preventing the potential of the word line from floating. The driver circuit includes an enhancement-type switching MOSFET and a depletion type resistor MOSFET connected in series. By virtue of the connection of a gate of the depletion type MOSFET, the depletion type MOSFET is always turned on so that whether or not the switching type enhancement MOSFET is turned on, the common connection between the switching MOSFET and the resistive MOSFET will always be at a prescribed potential thereby preventing the word driver line from floating.
Inventors:
SHIMADA SHUNJI
ITO TSUNEO
ITO TSUNEO
Application Number:
JP12924175A
Publication Date:
June 09, 1976
Filing Date:
October 29, 1975
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/41; G11C11/407; G11C11/413; G11C11/418; H03K17/687; H03K19/0185; (IPC1-7): G11C7/00; H03K17/56
Domestic Patent References:
| JPS4945649A | 1974-05-01 | |||
| JPS4968631A | 1974-07-03 | |||
| JPS4817227A |
Foreign References:
| US3510856A | 1970-05-05 |