Document Type and Number:
Japanese Patent JPS5410219
Kind Code:
B2
Abstract:
A microprogramming control system employing a plurality of low read rate control memories, for storing micro instructions, individually addressed in turn at a rate greater than the read rate of each memory. Each addressed control memory reads out a plurality of micro instructions. A selection circuit receives the plurality of micro instructions, in time shared fashion, read out in turn from each addressed control memory, then selects and gates a single micro instruction to a storage device. One portion of the selected micro instruction is designated as an address for the next micro instruction to be read out from the same control memory, and is accordingly gated to an address storage device at the input of the corresponding control memory.
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Application Number:
JP13921173A
Publication Date:
May 02, 1979
Filing Date:
December 07, 1973
Export Citation:
International Classes:
G06F9/28; G06F9/22; G06F9/26