Document Type and Number:
Japanese Patent JPS5527478
Kind Code:
B2
Abstract:
A method of making a multilayer board in which relatively thick ground and voltage planes are punched to form clearance holes. The planes are stacked with insulative layers, laminated and then drilled to produce through holes aligned with the clearance holes. The through holes are then plated-through. The method eliminates under-etch problems in thick ground and voltage planes which are capable of carrying high magnitudes of current.
Application Number:
JP11083075A
Publication Date:
July 21, 1980
Filing Date:
September 12, 1975
Export Citation:
International Classes:
H01R12/51; H05K1/02; H05K3/44; H05K3/46; H05K3/42