Document Type and Number:
Japanese Patent JPS5547416
Kind Code:
B1
Abstract:
An arithmetic unit in which a plurality of arithmetic and logic functions are performed using either one or both of two inputs X and Y, each input providing a variable number of bits in parallel. The output may be any one of a number of functions, such as the arithmetic functions of X + Y and X - Y, and the logical functions X.Y, X + Y, X (+) Y, X, and Y, etc. All of the functions are generated by the unit and any of the functions may be selected and operate as a data source. The arithmetic unit can operate either in a straight binary or a binary-coded decimal mode. The number of bits in the output for the arithmetic functions is variable and the carry or borrow is generated for each order and is therefore available from the highest order according to the selected length.
Application Number:
JP5894772A
Publication Date:
November 29, 1980
Filing Date:
June 12, 1972
Export Citation:
International Classes:
G06F7/494; G06F7/50; G06F7/575; (IPC1-7): G06F7/00; G06F7/38