Document Type and Number:
Japanese Patent JPS5637707
Kind Code:
B2
Abstract:
1425864 Semiconductor devices INTERNATIONAL BUSINESS MACHINES CORP 30 May 1973 [30 June 1972] 25830/73 Heading H1K In the manufacture of a semiconductor device including spaced conductive lines 44A, B, C constituted by strips of doped semiconductor material, a first non-conductive semiconductor layer 14, e.g. of polycrystalline Si, is deposited on a substrate which may comprise a SiO 2 film 12 on a p type monocrystalline Si body 10. A patterned mask 15A, B, C, D, e.g. of photo-etched silicon nitride, is provided on the layer 12 and a second non-conductive semiconductor layer 24, e.g. of polycrystalline Si, is deposited thereon. In the arrangement shown in Fig. 2 the layer 24 also fills two openings etched through the layers 14 and 12 to the body 10. Parts of the layers 24 and 15 may now be removed to leave patterns as in Fig. 4, and a dopant such as As or P is diffused or ion implanted into the remaining parts 44A-F of the layer 24 and also into the portions of the layer 14 not protected by the retained portion of the mask 15A, B, C, D. In the embodiment doped regions 36, 37 are simultaneously formed in the body 10. The resulting structure comprises a charge-coupled device having spaced conductive phase lines, and an IGFET having source and drain regions 36, 37 connected to conductors 44D, F, and a polycrystalline Si gate electrode 44E. The structure may be sealed in a layer of pyrolytic oxide.
Application Number:
JP5789673A
Publication Date:
September 02, 1981
Filing Date:
May 25, 1973
Export Citation:
International Classes:
H01L27/04; H01L21/00; H01L21/3205; H01L21/339; H01L21/822; H01L21/8234; H01L23/485; H01L23/52; H01L23/522; H01L27/148; H01L29/00; H01L29/417; H01L29/49; H01L29/762