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Title:
SAMPLE HOLDING CIRCUIT
Document Type and Number:
Japanese Patent JPS58115693
Kind Code:
A
Abstract:

PURPOSE: To obtain a high-precision sample holding output by inserting a diode which forms a short circuit between capacitors when a diode bridge turns off to prevent an input signal from appearing at an output terminal during a holding period.

CONSTITUTION: When the anode connection point between diode D1 and D3 is at a lower level than the cathode connection point between diodes D2 and D4, the diodes D1WD4 turn off a make to disconnection between an input terminal 10 and an output terminal 11, and charges in a capacitor 12 are held. A pulse voltage applied to terminals 13 and 14, on the other hand, turns on transistors (TR) 15B and 16A and turns off TRs 15A and 16B in a section T1 or turns on the TRs 15A and 16B and turns off the TRs 15B and 16A in a section T2; and those sections are repeated. In the section T2, diodes D5 and D6 turn on to flow a transient current through capacitors 17 and 18 to vary voltage Vc and VD to VA. Thus, voltages at points C and D cancel pulse voltage components appearing input and output terminals through the floating capacties of the diodes D1WD4 due to the voltage fluctuation equally to positively and negaively around VA, to prevent the generation of an error voltage component.


Inventors:
ISHIKAWA FUMIO
Application Number:
JP21411681A
Publication Date:
July 09, 1983
Filing Date:
December 28, 1981
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C27/02; H03K7/02; (IPC1-7): G11C27/02; H03K7/02
Attorney, Agent or Firm:
Masatomo Sugiura



 
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