3-INPUT COMPARATOR, SATURATION ARITHMETIC UNIT USING THE SAME AND ARITHMETIC METHOD THEREFOR

Title:

3-INPUT COMPARATOR, SATURATION ARITHMETIC UNIT USING THE SAME AND ARITHMETIC METHOD THEREFOR

Document Type and Number:

Japanese Patent JP3675111

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a 3-input comparator capable of realizing high-speed arithmetic operations in the arithmetic processing of saturation addition, saturation subtraction or saturation multiplication.
SOLUTION: In a saturation addition device, the processing of adding two inputs A and B in an adder 11 and the processing of determining whether or not the added result of the two inputs A and B deviates from a range determined by a prescribed reference value Ref in this 3-input comparator 12 are performed in parallel. By selecting and outputting one of the added result (sum) Sum and a prescribed saturation value Sat based on the determined result (compared result) in a selector 13, a saturation arithmetic operation is performed in the two stages of 'addition/comparison → selection'.

Inventors:

Koji Hirai

Application Number:

JP15463197A

Publication Date:

July 27, 2005

Filing Date:

June 12, 1997

Export Citation:

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Assignee:

ソニー株式会社

International Classes:

G06F7/38; G06F7/00; G06F7/50; G06F7/509; G06F7/533; (IPC1-7): G06F7/38; G06F7/00; G06F7/50

Domestic Patent References:

JP7281872A
JP5216622A
JP62266617A

Attorney, Agent or Firm:

Funabashi Kuninori

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