Title:
3D independent double gate flash memory
Document Type and Number:
Japanese Patent JP6084246
Kind Code:
B2
Abstract:
A memory device which can be configured for independent double gate cells storing multiple bits per cell comprises multilayer stacks of conductive strips configured as word lines. Active pillars are disposed between pairs of first and second stacks, and each active pillar comprises a vertical channel structure, a charge storage layer, and an insulating layer. The insulating layer in a frustum of the active pillar comes in contact with an arcuate edge of a first conductive strip in a layer of the first stack and an arcuate edge of a second conductive strip in the same layer of the second stack. A plurality of insulating columns divide the stacks of the word lines into even and odd lines coming in contact with opposing even and odd sides of each active pillar with the active pillars. The active pillar can generally have an elliptical shape with a long shaft disposed in parallel to the first and second conductive strips.
Inventors:
Han-Chin Lou
Application Number:
JP2015044848A
Publication Date:
February 22, 2017
Filing Date:
March 06, 2015
Export Citation:
Assignee:
Macronics International Company Limited
International Classes:
H01L27/115; G11C16/02; G11C16/04; H01L21/336; H01L29/788; H01L29/792
Domestic Patent References:
| JP2013008712A | ||||
| JP2011060991A | ||||
| JP2011165815A | ||||
| JP2011514013A |
Attorney, Agent or Firm:
Haruka International Patent Office