Title:
ＡＤ変換回路およびＡＤ変換方法
Document Type and Number:
Japanese Patent JP5869965
Kind Code:
B2
Abstract:
A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.
Inventors:
Masato Yoshioka
Chen Yang Fei
Tatsuya Ide
Chen Yang Fei
Tatsuya Ide
Application Number:
JP2012124578A
Publication Date:
February 24, 2016
Filing Date:
May 31, 2012
Export Citation:
Assignee:
富士通株式会社
株式会社ソシオネクスト
株式会社ソシオネクスト
International Classes:
H03M1/38; H03M1/16; H03M1/54
Domestic Patent References:
| JP2013150255A | ||||
| JP2012054913A | ||||
| JP2008244716A | ||||
| JP9069776A | ||||
| JP2014519793A |
Foreign References:
| WO2010109816A1 |
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto