Title:
ABNORMAL LOAD DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3555772
Kind Code:
B2
Abstract:
PURPOSE: To provide an abnormal load detecting circuit which can detect the short-circuit condition of a load irrespective of the kind and characteristic of a load driving element (tranistor) used and without breakdown of the transistor.
CONSTITUTION: An output side of a transistor 21 is connected to one end of a load 44 via a load driving terminal 43 and the other end of load 44 is connected to the power source voltage VB. The load driving terminal 43 is connected with a monitor circuit 22 for monitoring a voltage of the load driving terminal 43 and judging normal and abnormal state of the load 44. The input side of the transistor 21 is connected with a switching circuit 13 for switching a drive signal of the transistor 21 and a check signal which is inputted only when checking abnormal condition of the load 44 and the ON period of the check input signal is set shorter than the ON period of the drive signal.
Inventors:
Naoki Sakai
Application Number:
JP18151193A
Publication Date:
August 18, 2004
Filing Date:
July 22, 1993
Export Citation:
Assignee:
Fujitsu Ten Co., Ltd.
International Classes:
G05F1/56; H02H7/00; (IPC1-7): H02H7/00
Domestic Patent References:
| JP2107224U | ||||
| JP61004975A | ||||
| JP59079862A |
Attorney, Agent or Firm:
Ryuji Inuchi