Title:
ABSOLUTE VALUE CIRCUIT
Document Type and Number:
Japanese Patent JP2969203
Kind Code:
B2
Abstract:
PURPOSE: To provide an absolute value circuit suitable for analog type processing.
CONSTITUTION: This circuit is the combination of an analog type inversion circuit INVC and a maximizing circuit MAXC. The inversion circuit INVC uses an operational amplifier composed of cascade connected CMOS T1, T2 and T3 with gain '1' and the maximizing circuit MAXC connects the source follower output D4 and D5 of a pair of nMOS T4 and T5 to common output D0.
Inventors:
KOTOBUKI KOKURYO
YO KOREYASU
UIWATSUTO UONWARAUIPATSUTO
TAKATORI SUNAO
YAMAMOTO MAKOTO
YO KOREYASU
UIWATSUTO UONWARAUIPATSUTO
TAKATORI SUNAO
YAMAMOTO MAKOTO
Application Number:
JP25219692A
Publication Date:
November 02, 1999
Filing Date:
August 27, 1992
Export Citation:
Assignee:
TAKATORI IKUEIKAI KK
SHAAPU KK
SHAAPU KK
International Classes:
G01R19/22; G06G7/25; (IPC1-7): G06G7/25
Domestic Patent References:
| JP63128488A | ||||
| JP4975048A |
Attorney, Agent or Firm:
Yamamoto Makoto
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