Title:
ABSOLUTE VALUE DETECTING SIGNAL PROCESSING CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3135283
Kind Code:
B2
Abstract:
PURPOSE: To secure a dynamic range for a absolute value detecting signal processing circuit where the emitters of transistors are connected in common to each other by giving the input offset to the precedent stage of an absolute value detecting circuit through a compensating circuit to cancel the operating point shift and to eliminate the fluctuation of the operating point.
CONSTITUTION: The DC component of an input signal is cut by a capacitor 3. The inverse amplifiers 1 and 2 apply previously the input offset voltage VBE(8) with a PNP transistor(TR) 8 of an input stage and set the output voltage level at a voltage level secured by adding the voltage VBE(8) to the reference voltage VR. In an absolute value detecting circuit 4, the potential is reduced at a point A by the base-emitter voltage VBE(7) of an npn TR 7. Meanwhile the potential is reduced at a point B by the base-emitter voltage VBE(6) of an npn TR 6. Then the voltage VBE(8) is set at the levels equal to the VBE(6) and VBE(7) and these voltage levels are canceled. Thus the output voltage levels are set at the levels approximately equal to the VR.
Inventors:
Tatsuo Furukawa
Application Number:
JP15687191A
Publication Date:
February 13, 2001
Filing Date:
June 27, 1991
Export Citation:
Assignee:
Canon Inc
International Classes:
G01R19/04; G06G7/25; H03F1/30; (IPC1-7): G06G7/25
Domestic Patent References:
| JP195376A |
Attorney, Agent or Firm:
Keizo Nishiyama (1 person outside)