PURPOSE: To facilitate acess to a common-use memory by converting successive address outputted from plural arithmetic processors into unused addresses of plural storage areas of the common-use memory and supplying them to the common-use memory.

CONSTITUTION: Central processing unit CPUs 1W3 are connected to a DMA control circuit 4, which decides on priority among requests from the CPUs to allow the CPUs to operate. The CPUs are connected to an access controller 10 through buses 5W7 and a signal line 8. The controller 10 includes the common-use memory 12 and address conversion memory 11 used in common among the CPUs. The memory 12 is divided into plural segments and each CPU when to indicates an address of the memory 12 outputs successive addresses SG to SG the memory address bus 5 and the memory address to the memory address bus 6. The successive addressed SG are supplied to the memory 11, which converts the successive addresses into actual addresses of the memory 12 and outputs them.