To provide a system arrangement having an architecture in which a plurality of processors are connected to single memory unit.
The system arrangement has a memory unit, a bus, a first master and a second master. The memory unit has a memory interface in accordance with a handshake-free protocol, and the memory interface is located between the memory unit and an access master. The bus is electrically connected to the memory unit. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory access interface. The second master being configured to transfer an interrupt request to the first master before accessing the memory unit.
TASHER NIR
| JPH03116335A | 1991-05-17 | |||
| JPS60237566A | 1985-11-26 | |||
| JPS6159516A | 1986-03-27 | |||
| JP2003196251A | 2003-07-11 | |||
| JP2004528656A | 2004-09-16 |
Shinsuke Onuki
Tadashige Ito