PURPOSE: To avoid the noise from a logical operation circuit and to obtain an AD converter with high accuracy by staggering the timing of the sampling in a comparator of the AD converter from the operation timing of other logical operation circuits.

CONSTITUTION: A system clock , which controls a logical operation circuit part, is given as a reference signal by dividing an output F0 of an oscillation circuit, and a clock s', which controls a comparator of an AD converter which is in the same semiconductor chip with the logical operation circuit, is formed by using the system clock as a reference. The rising of the clock s' can be made so that it will avoid the noise by setting the time lag from the rising of the system clock .