Title:
加算器、およびその合成装置、合成方法、合成プログラム、合成プログラム記録媒体
Document Type and Number:
Japanese Patent JP4436412
Kind Code:
B2
Abstract:
A conventional multi-input adder has a problem that only either the number of stages of operation blocks or the number of half adders and full adders can be reduced. In order to solve the problem of the prior art, half adders (HA201, HA203, HA204, HA202, HA205) are used only in a position at a lower digit having two inputs in an operation block (2a), a position having five inputs and two carries from the lower digit in a stage three stages prior to a final-stage operation block (2d), and a position one stage prior to the final-stage operation block (2d).
Inventors:
Koichi Nagano
Application Number:
JP2007503698A
Publication Date:
March 24, 2010
Filing Date:
February 16, 2006
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G06F7/501; G06F7/506; G06F7/53
Domestic Patent References:
| JP10307706A | ||||
| JP2002118444A | ||||
| JP8179932A | ||||
| JP2004133861A |
Attorney, Agent or Firm:
Kenichi Hayase