Title:
ADDER AND SUBTRACTOR
Document Type and Number:
Japanese Patent JP3022731
Kind Code:
B2
Abstract:
PURPOSE: To provide an adder and a subtractor in which an input voltage range is widened with excellent linearity and which are operated at a low voltage.
CONSTITUTION: Figure indicates a MOS adder. Sources (emitters) of four transistors (TRs) forming two-sets of TR pairs (M1, M2) (M3, M4) are connected in common. In a quadri-tail cell driven by a common current source I0, a 1st signal (voltage V1) and a 2nd signal (voltage V2) are given differentially between gates (bases) of the two sets of TR pairs, and drains (collectors) are connected in common by adding or subtracting output currents at the output pairs to form the adder and subtractor.
Inventors:
Katsuji Kimura
Application Number:
JP19284494A
Publication Date:
March 21, 2000
Filing Date:
July 25, 1994
Export Citation:
Assignee:
NEC
International Classes:
G06G7/14; (IPC1-7): G06G7/14
Domestic Patent References:
| JP59103174A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
Previous Patent: ライターの給油タンク
Next Patent: POSTURE REVERSING SUPPLY MECHANISM OF COVER ASSEMBLING COMPONENT IN CYLINDRICAL ALKALINE BATTERY ASS...
Next Patent: POSTURE REVERSING SUPPLY MECHANISM OF COVER ASSEMBLING COMPONENT IN CYLINDRICAL ALKALINE BATTERY ASS...