To provide an addition operation by utilizing a memory array itself.

When an addition operation of each digit is to be performed about two pieces of binary data, the value of a binary input bit is preliminarily written in each memory cell MCa, MCb and MCc according to a normal writing procedure in a DRAM. After a bit line pair BLi and BLi- are precharged to reference voltage 0.5 VDD, each corresponding word line Wa, Wb and Wc is made active and the respective storage charge of the cell MCa, MCb and MCc are added up through a common bit line BLi. A 1st sense amplifier S/A1 performs a normal binary type detection amplification operation and outputs the binary data of '1' or '0' in accordance with the level relation between the potential Ve4 of the line BLi and comparison reference voltage Vref1. A 2nd sense amplifier S/A2 also performs a normal binary type detection amplification operation and outputs the binary data of '1' or '0' in accordance with the level relation between the potential Ve4 of the line BLi and comparison reference voltage Vref2. As a result, 2-bit binary data (Ve4 (MSB) and Ve4 (LSB)) are obtained by means of the amplifiers S/A1 and S/A2.