PURPOSE: To quickly convert an address without reducing the TLB hit rate even if an instruction and data are linked in the same entry, by providing two quick address conversion buffers (TLB), one for instruction and the other for operand.
CONSTITUTION: When a memory is accessed from a processor, the entries of a TLB 40 for instruction and a TLB 41 for operand are selected by the middle part 51 of a logical address 19 transferred through an interface circuit. If the access from the processor is in an instruction cycle, the upper part 45 of the TLB 40 for instruction and a page start address 47 are selected and outputted by selectors 42 and 43; and if the access is in an operand cycle, the upper part 46 of the TLB 41 for operand and a page start address 48 are selected and outputted by selectors 42 and 43. Since preparations for selection of selectors are terminated more early than entry read from TLBs 40 and 41, the time for selection is unnecessary.
| WO/2013/095525 | CONTENT-AWARE CACHES FOR RELIABILITY |
| WO/2015/075076 | MEMORY UNIT AND METHOD |
| JP5473438 | Methods for test case generation, information processing systems and computer programs |
ARAOKA MANABU
TAKATANI SOICHI
| JPS5812187A | 1983-01-24 | |||
| JPS5853075A | 1983-03-29 | |||
| JPS60168251A | 1985-08-31 |